The present invention relates to a substrate treating method for treating a substrate to be treated, such as a semiconductor substrate, in the condition where the substrate to be treated is supported by a support substrate, and a method of manufacturing a semiconductor apparatus by use of the substrate treating method.
In recent years, attendant on the demand for enhancement of the performances of electronic apparatuses and for reductions in the thickness and size of electronic apparatuses, the integration density and mounting density of electronic parts have been enhanced progressively, and semiconductor apparatuses of the MCM (Multi-Tip Module) or SIP (System-In-Package) type using the flip chip mounting have been coming to constitute a main stream. This kind of semiconductor apparatuses include those based on a configuration in which the flip chip mounting of a second semiconductor chip on a first semiconductor chip is adopted.
FIG. 3 is a sectional view showing a general configuration of this kind of semiconductor apparatus in the past. The semiconductor apparatus shown includes a first semiconductor chip 1 and a second semiconductor chip 2. The second semiconductor chip 2 is mounted on a substantially central area of a principal surface of the first semiconductor chip 1 by flip chip mounting in which a plurality of bumps 3 are used. In the periphery of the first semiconductor chip 1, a plurality of electrode pads 4 are formed in the manner of surrounding the region where the second semiconductor chip 2 is mounted. In addition, a dam 5 is provided between the chip mounting area and the forming region of the electrode pads 4, on the principal surface of the first semiconductor chip 1. The dam 5 is formed in a rectangular frame-like shape in plan view on the inner side of the forming region of the electrode pads 4 in such a manner as to surround the chip mounting region. Besides, the gap between the first semiconductor chip 1 and the second semiconductor chip 2 is filled with an underfill material 6.
The related-art semiconductor apparatus configured as above is adhered onto a mounting substrate 7 through an adhesive material layer 8 as shown in FIG. 3, and then electrical connection between the electrode pads 4 on the first semiconductor chip 1 and lands 9 on the mounting substrate 7 is made through bonding wires 10.
In recent years, in relation to such semiconductor apparatuses of the MCM or SIP type, there has been a demand for a higher signal processing speed, a smaller mounting area, and the like. Specifically, the semiconductor apparatus mounted by the wire bonding system shown in FIG. 3 has the problem of a delay in signal transfer due to the wiring length of the bonding wires 10 and the problem of securing the mounting area necessary for laying around the bonding wires 10.
In view of this, a configuration may be adopted in which, as schematically shown in FIG. 4, the first semiconductor chip 1 is provided with vias (through electrodes) 11 to establish inter-layer connection between the bumps 3 joined to the second semiconductor chip 2 on the upper layer side and bumps 12 joined to the mounting substrate 7 on the lower layer side. This configuration is very advantageous because it is thereby possible to simultaneously realize a higher signal processing speed and a smaller mounting area.
For forming the vias, it may be necessary to reduce the thickness of the wafer, in order to realize a shorter processing time and a reduced pitch. For thinning the wafer, back grinding has been practiced. Thus, as a method of forming vias, there has been known a method in which vias are buriedly formed from the face side of a wafer, and thereafter the back side of the wafer is ground so that terminal surfaces of the vias are exposed to the exterior (see Japanese Patent Laid-open No. 2004-241479).
Meanwhile, as the wafer thickness is reduced, the wafer becomes more liable to warp, and it becomes more difficult to handle the wafer. In view of this, it may be necessary to adhere a support substrate to the face side of the wafer, thereby enhancing the supportability of the wafer, and to appropriately remove the support substrate from the substrate to be treated, after the treatment of the substrate to be treated is completed.
As above-mentioned, the adhesive for adhesion between the support substrate and the wafer is necessary to have good temporary fixation performance for enduring the processing of the wafer and good stripping property for removal thereof after completion of the wafer processing. In relation to the technology of peeling (removing) the adhesive, there have been proposed, for example, a method of removing the adhesive by dissolution in a solvent, and a method of lowering the adhesiveness of the adhesive by irradiation with UV rays (see Japanese Patent Laid-open No. 2003-171624 and Japanese Patent Laid-open No. 2005-191550).
FIGS. 5A to 5J are step sectional views illustrating a method of manufacturing a semiconductor apparatus as a first related-art example.
First, as shown in FIG. 5A, there is prepared a wafer 100 in which a device layer 102 including semiconductor devices such as transistors, wirings 103, an insulating layer 104, and the like is formed on the face side of a substrate body (semiconductor substrate) 101 composed of silicon. Electrode pads 105 in conduction with parts of the wiring layer 103 are formed on the face side of the device layer 102, and a buried conductor layer 106P in conduction with parts of the wiring layer 103 is formed on the face side of the substrate body 101.
Next, as shown in FIG. 5B, solder bumps 107 are formed on the electrode pads 105 on the face side of the device layer 102. Subsequently, as shown in FIG. 5C, an adhesive is applied to the whole surface area of the device layer 102 inclusive of the solder bumps 107 to form an adhesive material layer 108, and a support substrate 109 is adhered onto the adhesive material layer 108. The support substrate 109 is composed of a glass substrate or silicon substrate provided therein with a plurality of through-holes 109a for supplying a stripping liquid.
Subsequently, as shown in FIG. 5D, in the condition where the wafer 100 is supported by the support substrate 109, the back side of the substrate body 101 is ground so as to thin the substrate body 101 to a predetermined thickness, and to expose tip portions 106a of the vias (buried conductor layer) 106 from the back side of the thinned substrate body 101t. Incidentally, though simplifiedly shown in the figure, the thinned substrate body 101t is in practice formed to be thicker than the device layer 102, and the support substrate 109 is in practice formed to be thicker than the substrate body 101t. In addition, in FIG. 5D and the latter figures, the wafer 101 is shown in the upside-down state (as compare with its posture in the former figures).
Thereafter, as shown in FIG. 5E, an insulating film 111 is formed on the back side of the substrate body 101t, and external connection terminals 112 are formed on the tip portions 106a of the vias 106. Then, as shown in FIG. 5F, semiconductor chips 113 are mounted on the external connection terminals 112 by flip chip mounting; thereafter, as shown in FIG. 5G, an underfill layer 114 is formed in the mounting areas of the semiconductor chips 113.
Next, as shown in FIG. 5H, the support substrate 109 is released (peeled) from the adhesive material layer 108. The support substrate 109 is released (peeled) by supplying a stripping liquid (e.g., alcohol) via the plurality of through-holes 109a formed in the inside of the support substrate 109 to thereby dissolve the adhesive material layer 108. Then, as shown in FIG. 5I, the adhesive material layer 108 is dissolved away, and thereafter the wafer 100 is diced on a chip basis, whereby semiconductor apparatuses 100A of a chip-on-chip structure having the vias (through electrodes) 106 as shown in FIG. 5J are manufactured.
In the next place, FIGS. 6A to 6I are step sectional views illustrating a method of manufacturing a semiconductor apparatus as a second related-art example. Incidentally, in the figures, the portions corresponding to those in the first related-art example described above are denoted by the same symbols as used above, and detailed descriptions of these portions will be omitted.
In this example of the related art, the steps of forming solder bumps 107 on the face side of a wafer 100 and thereafter adhering a support substrate are the same as those in the first related-art example (FIGS. 6A to 6C). It should be noted that this example differs from the first related-art example in that the support substrate 119 is adhered to the face side of the wafer 100 through an adhesive material layer 118 formed of an adhesive of which the adhesiveness is deteriorated by irradiation with UV rays. The support substrate 119 is composed of a glass substrate which is transparent to UV rays.
Then, like in the first related-art example, the steps of thinning a substrate body 101 (FIG. 6D), forming external connection terminals 112 (FIG. 6E), mounting semiconductor chips 113 (FIG. 6F), and forming an underfill layer 114 (FIG. 6G) are conducted. Thereafter, the step of irradiating the adhesive material layer 118 with UV rays through the support substrate 119 to thereby release (peel) the support substrate 119 from the wafer 100 is carried out (FIG. 6H). Then, the wafer 100 is diced on a chip basis, whereby semiconductor devices 100A of the chip-on-chip structure having the vias (through electrodes) 106 as shown in FIG. 6I are manufactured.